Low latency Network TAP IP-Core for full duplex 1OOM/1G Ethernet links

SCS-TAP is a Passive Network TAP IP-Core that gives a complete visibility of the traffic data on the contrary of SPAN ports (also called mirror ports) monitoring approach that is supported by most switch vendors.

SPAN Ports solution suffers from two main drawbacks (i) Lack of flexibility since the monitoring tool cannot be deployed at any network segment, (ii) Poor monitoring capability since SPAN ports have low priority. On the contrary, passive devices can be deployed permanently on any network link to provide a permanent access port to the network traffic and any analyzer tool can be connected to the tap any time without disrupting the network link.

In addition, there are three main considerations when choosing a network tap to monitor critical time-sensitive systems:

  • The tap shall ensure a reliable real-time full-duplex sniffing,
  • The tap should not compromise the system determinism,
  • The tap should not compromise the system synchronicity by adding too much latency to the network link or by adding too much jitter.

It is hard to reach this level of efficiency with any software-based network taps available on the market unless using very expensive CPUs and memory devices.

SCS-TAP is a full hardware designed network tap running on FPGA devices. To reach the required efficiency, SCS-TAP has been implemented to work at the MAC layer without any further protocols processing. SCS-TAP is an ideal tool for teams looking to deploy efficient monitoring for high performance networks such as time sensitive, deterministic, low latency, ...



  • Flexibility of use since the customer can use his own FPGA boards to build as much taps as needed,
  • Non-intrusive,
  • Support 100% full-duplex traffic (tested with several Millions consecutive frames),
  • low end-to-end latency inferior to 1 us (see Table 1),
  • preserve the system determinism because frames are handled in the same order than the mission network does
  • Sniffing of both correct and error frames,
  • Support all Ethernet 802.3 compliant standards: Etherfly, UDP/TCP IP, TSN, AFDX, Profinet, Powerlink, Ethercat, ModBusEthernet …
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Product description

  •  The Product is delivered as encrypted RTL source code with node locked license. For any other type of license, please contact us
  • Available on Arria 10, Cyclone 10, Stratix 10
  • For any other FPGA please contact us


For further details you can download the product sheet at the following address.